Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

1 June 1980

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-29 (6) , 527-531
https://doi.org/10.1109/tc.1980.1675614

Abstract

At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.

Keywords

MODELS
BEHAVIOR
LOGICAL
FUNCTIONAL
CIRCUITS
MOS
PARAMETRIC
VOLTAGE
TESTABILITY

This publication has 2 references indexed in Scilit:

Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
Bell System Technical Journal, 1978
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
IEEE Transactions on Electronic Computers, 1967