Design model for bulk CMOS scaling enabling accurate latchup prediction

1 March 1983

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 30 (3) , 240-245
https://doi.org/10.1109/t-ed.1983.21107

Abstract

The integration density of advanced bulk CMOS structures heavily depends on SCR type of latch up. Depending on the technology chosen the n-p-n-p-n-p interaction, which can be fired by noise, destroys tile stored information or even the chip itself. This paper presents the first complete two-dimensional numerical analysis for a typical CMOS structure including latchup path in the "OFF," "ON," "firing" and "sustaining" mode. Results and experimental data are discussed and used to develop a simplified, yet accurate CMOS design model. This allows the calculation of the firing and sustaining edge depending on geometrical and processing data.

Keywords

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