SOM hardware with acceleration module for graphical representation of the learning process
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A digital hardware implementation of self-organizing maps is presented. Dedicated hardware is implemented that allows the on-line visualization of the map during learning. The use of a scalable parallel architecture enables the realization of large scale high performance maps. Fist silicon was produced in a 0.8 mm, 2 metal layer CMOS technology, implementing about 161,800 transistors on a die size of 28.58 mm 2 . Experimental results are presented, that prove the functionality of the design up to a clock frequency of 40 MHz. A classification rate of 250,000 vectors per second and an adaptation rate of 94,000 vectors per second can be guaranteed, independent from the size of the network.Keywords
This publication has 6 references indexed in Scilit:
- Artificial Neural Network (ANN)-Based Model for In Situ Prediction of Porosity of Nanostructured Porous SiliconMaterials and Manufacturing Processes, 2008
- A scalable processor array for self-organizing feature mapsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- SOM accelerator systemNeurocomputing, 1998
- System identification using selforganizing feature mapsPublished by Institution of Engineering and Technology (IET) ,1997
- Self-Organizing MapsPublished by Springer Nature ,1995
- A hybrid knowledge processing architecturePublished by Institution of Engineering and Technology (IET) ,1994