An analog CMOS Viterbi detector for digital magnetic recording
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A fully-integrated analog Viterbi detector is presented. Four chips, each containing two VA (Viterbi algorithm) dicode detectors, have been fabricated in the standard 2- mu m, double-poly, p-well MOSIS CMOS process. By externally interleaving the two-dicode outputs, each part operates at over 40 Mb/s on a PR class IV (PR4) channel. The chip consumes under 100 mW from a single 5-V supply. The active area is 1.8 mm*1.8 mm (2.2 mm*2.2 mm with pads). Two main functions are implemented by the Viterbi detector: (1) metric calculation and (2) survivor sequence storage (path memory). The path memory is straightforward, digital, and is designed using true single-phase clocked flip-flops.Keywords
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