Storage array and sense/refresh circuit for single-transistor memory cells

1 January 1972

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XV, 56-57
https://doi.org/10.1109/isscc.1972.1155066

Abstract

The read signals of dynamic single-transistor MOS memory cells decrease with decreasing cell area. This paper will discuss a noise-compensating array and sensitive refresh amplifiers allowing a minimum cell area of 1600 μm²(2.6 mil²).

Keywords

VOLTAGE
PARASITIC CAPACITANCE
VIDEO RECORDING
CAPACITORS
CIRCUIT ANALYSIS COMPUTING
SILICON
ELECTRODES
MOSFETS
TRANSISTORS
SOLID STATE CIRCUITS

This publication has 1 reference indexed in Scilit:

Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions
Solid-State Electronics, 1966