A high-performance silicided amorphous-silicon contact and interconnect technology (HPSAC) for VLSI is presented. In this novel scheme, a patterned silicide layer is used to form self-aligned contacts to the source/drain regions, as well as to interconnect devices. The fabrication procedures and some key processing techniques are described, Experimental results on n-and p-channel MOSFET's fabricated with HPSAC technology are presented. The performance improvement due to reduction of parasitic capacitance and resistance is discussed.