Hardware implementation of fair queuing algorithms for asynchronous transfer mode networks
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Communications Magazine
- Vol. 35 (12) , 54-68
- https://doi.org/10.1109/35.642834
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
- Efficient network QoS provisioning based on per node traffic shapingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- WF/sup 2/Q: worst-case fair weighted fair queueingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Latency-rate servers: a general model for analysis of traffic scheduling algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A self-clocked fair queueing scheme for broadband applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A general methodology for designing efficient traffic scheduling and shaping algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Rate-proportional servers: a design methodology for fair queueing algorithmsIEEE/ACM Transactions on Networking, 1998
- A reconfigurable hardware approach to network simulationACM Transactions on Modeling and Computer Simulation, 1997
- Efficient fair queuing using deficit round-robinIEEE/ACM Transactions on Networking, 1996
- Service disciplines for guaranteed performance service in packet-switching networksProceedings of the IEEE, 1995
- VirtualClockACM Transactions on Computer Systems, 1991