Strategies in a cost-effective implementation of the PDC half-rate codec for wireless communications

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1 (10903038) , 203-207
https://doi.org/10.1109/vetec.1996.503437

Abstract

An application specific 16-bit fixed-point DSP (AK 2377) has been developed which executes the PDC (Personal Digital Cellular) half-rate speech codec system, an 80 MOPS task, at only 20 MHz operation with a low-power consumption of 100 mW. This was achieved through an architecture which hosts a customized parallel data path with a low memory bandwidth, customized I/O, a VLIW-like instruction set, and software innovations to minimize the complexity requirements.

Keywords

WIRELESS COMMUNICATION
DIGITAL SIGNAL PROCESSING CHIPS
DIGITAL SIGNAL PROCESSING
SPEECH CODECS
COMPUTER ARCHITECTURE
TECHNOLOGICAL INNOVATION
READ ONLY MEMORY
ENERGY CONSUMPTION
CLOCKS
SOFTWARE DESIGN

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