Trenched Schottky barrier PMOS for latchup resistance
- 1 August 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 5 (8) , 293-295
- https://doi.org/10.1109/EDL.1984.25922
Abstract
A new CMOS technology for VLSI applications has been developed. It provides latchup resistance, good performance, reduced source/drain resistance, and allows the use of shallower junctions with little increase in technological complexity. The key feature of this new structure is the realization of a self-aligned diffused lateral ring around the Schottky PMOS source and drain (S/D) that combines the advantages of the diffused technology with the latchup resistance of the Schottky source and drain.Keywords
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