A triple-level wired 24K gate CMOS gate array

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVIII, 122-123
https://doi.org/10.1109/isscc.1985.1156854

Abstract

This paper will describe an array using adjacent double transistor columns and 2μ design rules for a 12.8×12.8mm²chip. Implementation of a digital signal processor with 19.3K gates of RAM, multiply, ALU and control logic will be compared with a full custom design.

Keywords

WIRING
LOGIC CIRCUITS
DIGITAL SIGNAL PROCESSORS
PROCESS DESIGN
LARGE-SCALE SYSTEMS
LOGIC ARRAYS
SIGNAL DESIGN
JOINING PROCESSES
ROUTING

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