On routine implementation of virtual evolvable devices using COMBO6
- 12 November 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification. The approach generates the implementation of a virtual reconfigurable circuit and evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3 - 3-bit multipliers. The COMBO6 card is employed for these experiments.Keywords
This publication has 11 references indexed in Scilit:
- Towards evolvable IP cores for FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Evolving circuits in seconds: experiments with a stand-alone board-level evolvable systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Prototyping a GA Pipeline for complete hardware evolutionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Towards the automatic design of more efficient digital circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Evolving an adaptive digital filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Evolution of analog circuits on field programmable transistor arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A High-Performance, Pipelined, FPGA-Based Genetic Algorithm MachineGenetic Programming and Evolvable Machines, 2001
- A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-CGenetic Programming and Evolvable Machines, 2001
- GeneticFPGA: a java-based tool for evolving stable circuitsPublished by SPIE-Intl Soc Optical Eng ,1999
- Real-world applications of analog and digital evolvable hardwareIEEE Transactions on Evolutionary Computation, 1999