Custom VLSI Electrical Rule Checking in an Intelligent Terminal
- 1 January 1981
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An extension to a language-based custom VLSI design approach is proposed in which the designer supplies just enough up-front semantic information to allow a substantial amount of beneficial design consistency checking with a minimum of computation. The computational load is reduced by using a bottom-up hierarchical design approach, with incremental checking as the design is built. The load is also reduced by imposing minor restrictions upon the layout designer, by requiring that all active elements be prechecked, and by attaching "type" attributes to interconnecting signals. The method is very efficient for highly "regular" designs. Checks performed are geometrical design rules, connectivity, static electrical consistency, and node rise-and-fall times.Keywords
This publication has 3 references indexed in Scilit:
- Verification of timing constraints on large digital systemsPublished by Association for Computing Machinery (ACM) ,1980
- Bristle Blocks: A Silicon CompilerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- SCALD: Structured Computer-Aided Logic DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978