Defect-tolerant interconnect to nanoelectronic circuits: internally redundant demultiplexers based on error-correcting codes

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Abstract
We describe a family of defect-tolerant demultiplexers based on error-correcting codes. A conventional demultiplexer with a k-bit input address and 2k -bit output may be fortified against certain defect types by widening its address bus to n > k bits to permit an encoded address to be used within the demultiplexer. The redundant address is computed by an encoder that guarantees a minimum Hamming distance d between addresses, which sparsely populate an expanded addres ss pace. The increased Hamming distances between addresses are especially tolerant of stuck-open defects (and broken wires, which are equivalent to multiple stuck-open defects). For each address width k ,t here are a series of demultiplexer designs with increasing internal redundancy, increasing d ,a nd increasing capability for defect tolerance. These circuit designs are especially suitable for nano-scale crossbars; in particular, they may be realized at the interface where the CMOS wires of conventional microelectronics cross nano-wires to form a mixed-scale interconnect crossbar. Thus, a small number (2n) of CMOS wires may be used to control a much larger number (2k ) of nano-wires; the family of encoded demultiplexer designs provides a robust interface to the nano-circuitry, giving significant protection from manufacturing mistakes at the cost of a relatively small amount of area overhead f A ∼ = n k .T his is a qualitatively new application of error-correcting codes, the analysis of which combines elements of the conventional coding-theoretic notions of full-error and erasure correction. In particular, a code with minimum distance d guarantees tolerance to up to d − 1d efects per nano-wire, in analogy to conventional erasure correction.