Systolic Arrays for Matrix Transpose and Other Reorderings

1 January 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-36 (1) , 117-122
https://doi.org/10.1109/tc.1987.5009457

Abstract

In this correspondence, a systolic array is described for computing the transpose of an n × n matrix in time 3n - 1 using n² switching processors and n² bit buffers. A one-dimensional implementation is also described. Arrays are also given to take a matrix in by rows and put it out by diagonals, and vice versa.

Keywords

PROGRAM PROCESSORS
DATA MINING
PROBABILITY DENSITY FUNCTION
SWITCHES
ARRAY SIGNAL PROCESSING
COMPUTATIONAL MODELING

This publication has 2 references indexed in Scilit:

Graph Problems on a Mesh-Connected Processor Array
Journal of the ACM, 1984
Numerically Stable Solution of Dense Systems of Linear Equations Using Mesh-Connected Processors
SIAM Journal on Scientific and Statistical Computing, 1984