Network subsystem design
- 1 July 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Network
- Vol. 7 (4) , 8-17
- https://doi.org/10.1109/65.224051
Abstract
It is argued that the bandwidth of the CPU/memory data path on workstations will remain within the same order of magnitude as the network bandwidth delivered to the workstation. This makes it essential that the number of times network data traverses the CPU/memory data path be minimized. Evidence which suggests that the cache cannot be expected to significantly reduce the number of data movements over this path is reviewed. Hardware and software techniques for avoiding the CPU/memory bottleneck are discussed. It is concluded that naively applying these techniques is not sufficient for achieving good application-to-application throughput; they must also be carefully integrated. Various techniques that can be integrated to provide a high bandwidth data path between I/O devices and application programs are outlined.Keywords
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