Extreme scaling with ultra-thin Si channel MOSFETs

26 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 267-270
https://doi.org/10.1109/iedm.2002.1175829

Abstract

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Keywords

MOSFETS
IMPLANTS
THRESHOLD VOLTAGE
DOPING
RING OSCILLATORS
OXIDATION
DIELECTRICS
RESEARCH AND DEVELOPMENT
MICROELECTRONICS
FABRICATION

This publication has 1 reference indexed in Scilit:

Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain
IEEE Electron Device Letters, 2001