100 nm gate aperture field emitter arrays
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 130-131
- https://doi.org/10.1109/ivmc.1998.728676
Abstract
We report the results of experimental and numerical simulation studies of the scaling of FEA gate apertures. Numerical simulation of "realistic" device structures was performed using a commercially available electrostatic simulator and custom written software. Our device simulations indicate that FEAs will operate with a gate to emitter voltage below 15 V if the gate aperture is scaled to 100 nm. At this operating voltage the FEA can provide an array current density of at least 10 /spl mu/A/cm/sup 2/ which should be adequate for use in a notebook computer type flat panel display.Keywords
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