Design methodology for GMICRO/500 TRON microprocessor
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 253-257
- https://doi.org/10.1109/iccd.1993.393371
Abstract
Describes the design methodology used for the architecture of the GMICRO/500 TRON CISC superscalar microprocessor. Its minimum performance goal is 50 MHz, 100 VAX-MIPS at 5 V. This severe goal and the CISC superscalar architecture make the design time long and require a lot of manpower and computer resources. The C language and Unix environment are used to reduce the cost of the logic simulation. Synopsis and GDT are used to accelerate the logic design and the cell/macro design. A supercomputer is used to shorten the gate-level simulation time. The total design manpower is under 603 man-months.<>Keywords
This publication has 3 references indexed in Scilit:
- GMICRO/500 microprocessor: pipeline structure of superscalar architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Design methodology for a MIPS compatible embedded control processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A CMOS 50 MHz CISC superscalar microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993