VLSI architectures for the hierarchical block-matching algorithm for HDTV applications

1 September 1990

proceedings article
Published by SPIE-Intl Soc Optical Eng

Vol. 1360, 398-410
https://doi.org/10.1117/12.24227

Abstract

This paper describes VLSI-architectures for HDTV-suitable implementations of two well-known hierarchical block-matching algorithms: the three-step search algorithm and the one-at-a-time search algorithm. The architectures exploit the regularity and design efficiency of systolic arrays, combined with a decision-driven on-chip data handling. They are capable of treating (16*16)-blocks, with a maximum displacement of +/-14 pixels, at 50MHz pixel rate. Another important feature is the small input-data bandwidth, which keeps to a minimum the requirements to external memory units. Transistor count and chip area estimations show that the architectures can be realized with today's CMOS technologies.

Keywords

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