Characteristics of sub-half-micrometre-gate self-aligned GaAs FET by ion implantation

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Abstract
A submicrometre-gate self-aligned GaAs FET was fabricated using a flash-annealing technique which could suppress the lateral diffusion of impurities from source and drain n+ regions within about 0.1 μm. The transconductance kept on increasing with the decrease in gate length up to the submicrometre length range. The highest intrinsic transconductance was 315 mS/mm at Lg = 0.44 μm. The threshold voltage and the drain conductance showed large shifts in the sub-half-micrometre-gate length range.