Transient Radiation Upset Simulations of CMOS Memory Circuits

1 January 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 31 (6) , 1337-1343
https://doi.org/10.1109/tns.1984.4333507

Abstract

A computer simulation technique has identified and modeled a dominant mechanism for transient ionizing radiation induced logic upset in certain CMOS integrated circuits. This mechanism, termed 'rail span collapse' here, has accounted for the discrepancy between simulated upsets of these circuits using only local radiation induced photocurrents and the experimentally observed upset dose-rate levels.

Keywords

CIRCUIT SIMULATION
CMOS MEMORY CIRCUITS
COMPUTATIONAL MODELING
CMOS LOGIC CIRCUITS
COMPUTER SIMULATION
INTEGRATED CIRCUIT MODELING
SEMICONDUCTOR DEVICE MODELING
IONIZING RADIATION
CMOS INTEGRATED CIRCUITS
RAILS

This publication has 2 references indexed in Scilit:

Transient Response Model for Epitaxial Transistors
IEEE Transactions on Nuclear Science, 1983
The Transient Response of Transistors and Diodes to Ionizing Radiation
IEEE Transactions on Nuclear Science, 1964