Insulated gate field effect transistors fabricated using the gate as source-drain mask

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Abstract
Conventional construction of an IGFET involves diffusing the source-drain junctions, then placing the gate over the channel area. To insure modulation of the entire channel area the gate must overlap the source and drain by an amount required by mask alignment tolerance. This overlap adds undesirable parasitic capacitance from source to gate and drain to gate. In this paper, two methods of forming the source-drain junction using the gate itself as the channel mask are described. These methods eliminate the gate alignment problem and therefore simplify fabrication and greatly reduce the parasitic gate capacitance. The first method uses ion implantation to form the source drain junctions. The metal gate structure is fabricated prior to the formation of the source and drain. The metal gate then acts as a mask against implantation doping in the channel region. Furthermore, the source and drain junctions are automatically placed for minimum gate to source-drain overlap. This technique is applicable to ion implantation because of the low temperature nature of this doping process. If a polycrystalline silicon film replaces the metal gate, conventional diffusion technique can be applied to this technique. Comparable structures were fabricated using conventional techniques and both of-the methods described here. The characteristics of each of these devices will be discussed.

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