A high-speed low-power Hi-CMOS 4K static RAM

1 June 1979

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 26 (6) , 882-885
https://doi.org/10.1109/T-ED.1979.19513

Abstract

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.

Keywords

CMOS
LOW POWER
SPEED
CIRCUIT
4K STATIC RAM

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