A high-performance N-channel MOSLSI using depletion-type load elements
- 1 June 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 7 (3) , 224-231
- https://doi.org/10.1109/jssc.1972.1050281
Abstract
A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.Keywords
This publication has 2 references indexed in Scilit:
- DSA enhancement—Depletion MOS ICPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1970
- The silicon insulated-gate field-effect transistorProceedings of the IEEE, 1963