Automated generation of DSP program development tools using a machine description formalism

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1 (15206149) , 457-460 vol.1
https://doi.org/10.1109/icassp.1993.319154

Abstract

The authors introduce a retargetable microcode generator for application specific digital signal processors (ASDSPs). The primary goal is to provide quickly system architects with the set of tools necessary for program development (assemblers, instruction set simulators, debuggers, and compilers), particularly when the processor architecture is refined simultaneously with the algorithm. After a modification of the architecture, only the machine description written in the language nML must be altered; the tools are then produced automatically. The machine description need not explicitly list every possible instruction in full length. Instead, a derivation tree is described. Through the extensive use of inheritance and sharing of properties, this description can be very compact. Based on the latter, the recognition of critical data paths and the analysis of machine inherent parallelism is solely performed by the tool generator.

Keywords

This publication has 5 references indexed in Scilit:

Combined scheduling and data routing for programmable ASIC systems
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
Open-ended system for high-level synthesis of flexible signal processors
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
BURG
ACM SIGPLAN Notices, 1992
Retargetable Compiler Code Generation
ACM Computing Surveys, 1982
Local Microcode Compaction Techniques
ACM Computing Surveys, 1980