A high-performance MOS technology for 16K static RAM

1 January 1979

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1979.189623

Abstract

A scaled double-poly MOS technology has been developed which features a static memory cell size of 1.5 mil2with 4µ design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400Å and poly-Si channel length to 2.1µ with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.

Keywords

READ-WRITE MEMORY
RANDOM ACCESS MEMORY
MOS DEVICES
DOPING
GRAPHICS
CIRCUIT SYNTHESIS
ELECTRONS
PRINTING
INTEGRATED CIRCUIT INTERCONNECTIONS
PRINTERS

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