A Statistical Approach to the Computation of Delays in Logic Circuits

1 April 1969

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-18 (4) , 320-328
https://doi.org/10.1109/t-c.1969.222659

Abstract

This paper describes a method whereby multiple regression techniques are used to predict the delay between input and output signals through a combinatorial logic chain.

Keywords

CIRCUITS
INPUT
COMBINATORIAL
OUTPUT
STATISTICAL APPROACH
PAPER DESCRIBES
COMPUTATION OF DELAYS
LOGIC CHAIN

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