A graph based processor model for retargetable code generation
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 102-107
- https://doi.org/10.1109/edtc.1996.494133
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Instruction set definition and instruction selection for ASIPsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal code generation for embedded memory non-homogeneous register architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Describing instruction set processors using nMLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Verification of hardware descriptions by retargetable code generationPublished by Association for Computing Machinery (ACM) ,1989
- Local Microcode Compaction TechniquesACM Computing Surveys, 1980
- Optimal Code Generation for Expression TreesJournal of the ACM, 1976