Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems

Abstract
[[abstract]]The authors propose a fully pipelined architecture to compute the 2-D discrete cosine transform (DCT) from a frame-recursive point of view. Based on this approach, two real-time parallel lattice structures for successive frame and block 2-D DCT are developed. These structures are fully pipelined with throughput rate N clock cycles for an N × N successive input data frame. Moreover, the resulting 2-D DCT architectures are modular, regular, and locally connected and require only two 1-D DCT blocks that are extended directly from the 1-D DCT structure without transposition. It is therefore suitable for VLSI implementation for high-speed HDTV systems. A parallel 2-D DCT architecture and a scanning pattern for HDTV systems to achieve higher performance is proposed. The VLSI implementation of the 2-D DCT using distributed arithmetic to increase computational efficiency and reduce round-off error is discussed.[[fileno]]2030234010002[[department]]資訊工程學

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