A high performance CBiCMOS with novel self-aligned vertical PNP transistors
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes a vertical PNP transistor with a novel self-aligned structure and a complementary BiCMOS process which makes use of it. The PNP's emitter electrode is formed at the same fabrication step as that of a self-aligned NPN's base electrode, and the base electrode is formed at the same fabrication step as that of the self-aligned NPN's emitter electrode. The PNPs have been fabricated adding only one photo-mask and one doping step to the BiCMOS processes. The maximum cutoff frequency or PNP and NPN transistors are 4.2 GHz and 20 GHz, respectively. The MOS transistors are compatible with simple CMOS devices.Keywords
This publication has 3 references indexed in Scilit:
- High performance LSI process technology: SST CBi-CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High Performance Complementary Bipolar TechnologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- High-speed low-power AC-coupled complementary push-pull ECL circuitIEEE Journal of Solid-State Circuits, 1992