The use of submicrometer electron-beam lithography for fabricating 4-kbit CCD memory arrays

Abstract
A 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features. The basic CCD cell size is 3.2 µm × 4.2 µm consisting of a storage area 2.4 µm × 3.6 µm with a 0.8-µm barrier and a 0.6-µm channel stop. To make these small CCD's, as well as the associated short-channel MOSFET's, we modified the conventional MOS wafer processing. The new process for two-level polysilicon gates requires six electron-beam levels with a minimum resist feature of 0.3 µm. Alignment of the electron-beam patterns uses Ta benchmarks which we found to be compatible with MOS devices. Testing of the 4-kbit array and other shift resisters showed submicrometer channel-stops and barriers are feasible while maintaining low channel-to-channel crosstalk and charge-transfer efficiency greater than 0.9995. In addition, low capacitance output circuits defined by electron-beam lithography can detect the small number of charges in the high-resolution CCD's and amplify the signal sufficiently to recirculate the data.

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