Co-Synthesis to a Hybrid RISC/FPGA Architecture

• 1 January 2000
• journal article
• Published by Springer Nature in Journal of Signal Processing Systems
• Vol. 24  (2/3) , 165-180
• https://doi.org/10.1023/a:1008141305507

Abstract

Keywords

• CLOCK CYCLE
• FIELD PROGRAMMABLE GATE ARRAY
• DEPENDENCY GRAPH
• NAPA
• RISC PROCESSOR