Reduction of Connections for Multibus Organization
- 1 August 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-32 (8) , 707-716
- https://doi.org/10.1109/TC.1983.1676308
Abstract
The multibus interconnection network is an attractive solution for connecting processors and memory modules in a multiprocessor with shared memory. It provides a throughput which is intermediate between the single bus and the crossbar, with a corresponding intermediate cost.Keywords
This publication has 3 references indexed in Scilit:
- Bandwidth of Crossbar and Multiple-Bus Connections for MultiprocessorsIEEE Transactions on Computers, 1982
- M-users B-servers arbiter for multiple-busses multiprocessorsMicroprocessing and Microprogramming, 1982
- Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer SystemIEEE Transactions on Computers, 1979