Impact of technology parameters on inverter delay of UTB-SOI CMOS
- 1 January 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 176-178
- https://doi.org/10.1109/soi.2002.1044466
Abstract
Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In this paper we analyse the impact of different parameters such as doping profile, gate work function and local interconnects on the inverter delay. For that purpose we have simulated fully-depleted (FD) SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation.Keywords
This publication has 2 references indexed in Scilit:
- An adjustable work function technology using Mo gate for CMOS devicesIEEE Electron Device Letters, 2002
- Ultrathin-body SOI MOSFET for deep-sub-tenth micron eraIEEE Electron Device Letters, 2000