Parasitic bulk resistances in junction-gate FETs

1 January 1967

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 55 (11) , 2031-2032
https://doi.org/10.1109/PROC.1967.6049

Abstract

A practical method for evaluating parasitic bulk resistances in junction FETs is described. The method does not require a knowledge of the actual device geometry or dimensions. It is shown that parasitic bulk resistances make up a substantial portion of measured open-channel resistance.

Keywords

FETS
ELECTRICAL RESISTANCE MEASUREMENT
GEOMETRY
CONTACT RESISTANCE
ITERATIVE ALGORITHMS
SAMPLING METHODS
CONTROL SYSTEMS
ARTIFICIAL INTELLIGENCE
FREQUENCY
RESISTORS

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