A phase-locked loop clock generator for a 1 GHz microprocessor
- 1 January 1998
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The design of a fully-integrated phase-locked loop (PLL) clock generator for a 1.0 GHz microprocessor using a 1.8 V, 0.25 /spl mu/m digital CMOS6X process is described. Hardware measurements are included, showing low jitter (</spl plusmn/36 ps active processor, </spl plusmn/9 ps quiet), high maximum lock frequency (1560 MHz), and wide lock range (1.9:1).Keywords
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- A 433 MHz 64 b quad issue RISC microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.0 GHz single-issue 64 b powerPC integer processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002