25 ps/gate GaAs standard cell LSIs using 0.5 mu m gate MESFETs
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A design system of GaAs standard cell LSIs using 0.5- mu m MESFETs is presented. This design system is intended to be used to design LSIs whose operating speed is from several hundred MHz to several GHz. A basic gate is DCFL (direct coupled FET logic), and the delay time is less than 25 ps. The library includes 40 cells and 8 I/O buffers which are designed to be compatible with ECL 10 K, TTL (transistor-transistor logic), CMOS, and GaAs. Using this design system, an LSI was fabricated, and its performance was evaluated. The results of the evaluation show that the error in postlayout simulation is under 10%.<>Keywords
This publication has 2 references indexed in Scilit:
- A high performance GaAs gate array familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A fully differential high speed, high fidelity cross point switch family designed with SCFL standard cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002