Selectively grown vertical Si- p MOS transistorwith short channel lengths
- 15 February 1996
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 32 (4) , 406-407
- https://doi.org/10.1049/el:19960248
Abstract
Vertical p-MOS transistors with channel lengths of ~130 nm have been fabricated using selective LPCVD epitaxy for the definition of the channel region, instead of fine line lithography. Owing to self-aligned facet growth the channel region and the volume diode which limited the parasitic bipolar transistor can be designed more independently. Thus a short-channel p-MOS transistor with a high breakthrough voltage, an ideal subthreshold behaviour and a high transconductance was fabricated.Keywords
This publication has 1 reference indexed in Scilit:
- Vertical MOS technology with sub-0.1 µm channellengthsElectronics Letters, 1995