A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology
- 1 May 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (5) , 788-794
- https://doi.org/10.1109/4.841508
Abstract
This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW.Keywords
This publication has 4 references indexed in Scilit:
- A 900 MHz CMOS LC-oscillator with quadrature outputsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.8 GHz CMOS voltage-controlled oscillatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A fully integrated CMOS DCS-1800 frequency synthesizerIEEE Journal of Solid-State Circuits, 1998
- A wide-bandwidth low-voltage PLL for PowerPC microprocessorsIEEE Journal of Solid-State Circuits, 1995