Three-dimensional shared memory fabricated using wafer stacking technology

11 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 81, 165-168
https://doi.org/10.1109/iedm.2000.904284

Abstract

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Keywords

STACKING
BROADCASTING
TESTING
READ-WRITE MEMORY
WAFER BONDING
RANDOM ACCESS MEMORY
FABRICATION
MACHINE INTELLIGENCE
SYSTEMS ENGINEERING AND THEORY
PARALLEL PROCESSING

This publication has 2 references indexed in Scilit:

A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology Using Adhesive Injection Method
Japanese Journal of Applied Physics, 1999
Future system-on-silicon LSI chips
IEEE Micro, 1998