The IC yield problem: A tentative analysis for MOS/SOS circuits

1 August 1978

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 25 (8) , 939-944
https://doi.org/10.1109/t-ed.1978.19205

Abstract

Yield on integrated circuits is the result of the contribution of many parameters including number of masking steps, design dimensions, and intrinsic process steps. Test vehicles specific to each process to be investigated are used and through ring oscillators yield figures, and test pattern results, evaluation of yield, as well as identification of main causes of yield loss can be made. The test vehicle approach is consistent with actual LSI circuits yield figures. Defect densities for SOS and bulk processes are compared showing that they are mainly dependent upon the number of critical masking steps and design dimensions.

Keywords

This publication has 2 references indexed in Scilit:

Defect density distribution for LSI yield calculations
IEEE Transactions on Electron Devices, 1973
A new look at yield of integrated circuits
Proceedings of the IEEE, 1970