An 820 pin PGA for ultra large-scale BiCMOS devices

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 396-404
https://doi.org/10.1109/ectc.1993.346816

Abstract

A high pin count, high performance PGA has been developed for next-generation ASIC devices which apply half-micron BiCMOS technology and have a maximum usable gate count of 300 K. In view of the advances in CMOS and BiCMOS ULSI technologies, high performance packages are required. This new package has been designed with due consideration of all package functions. Packages for high-end devices need to satisfy the following requirements: high electrical performance, low thermal resistance and high pin count in keeping with easy routing of PWB. The body size of the developed package is 60×60 mm 2 . Surface mount type pin joint was adopted to realize high wiring density of a printed wiring board. This package has 820 pins with 50 mil pitch, and 5 rows. A small pin diameter of 0.2 mm and a short pin length of 3.0 mm were used for surface mounting Author(s) Hiruta, Y. Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan Hirano, N. ; Itoh, K. ; Yamaji, Y. ; Kato, K. ; Motoyama, Y. ; Ohno, J. ; Homma, R. ; Kojima, S. ; Sudo, T.

Keywords

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