A transistor fault model for nMOS combinational circuits
- 30 June 1991
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 22 (4) , 15-26
- https://doi.org/10.1016/0026-2692(91)90003-6
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- MOS Test Pattern Generation Using Path AlgebrasIEEE Transactions on Computers, 1987
- Automated Testing of LSIComputer, 1982