A general consistency technique for increasing the controllability of high level synthesis tools
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A technique is introduced that gives an engineer greater control over the design space considered by a high level synthesis tool. This is accomplished by allowing the engineer to make assertions about temporal and structural relationships between operations in a data-flow graph that must be reflected in any synthesized result. An engineer can use these assertions to make design trade-offs and improvements while working with a high-level synthesis tool. Author(s) Arnstein, L.F. ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA Thomas, D.Keywords
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