Integrated bipolar master/slave D-flip-flop with multiplexing capability for Gbit/s operation

19 July 1984

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 20 (15) , 628-630
https://doi.org/10.1049/el:19840432

Abstract

A versatile integrated bipolar circuit developed for a broadband communication system is described. It consists of a master/slave D-flip-flop with a 2:1 time-division multiplexer at the input and a powerful buffer stage at the output. Despite realisation in a relatively simple bipolar technology, bit rates up to 1.5 Gbit/s (NRZ) were measured.

Keywords

BUFFER STAGE
MASTER/SLAVE D-FLIP-FLOP
BROADBAND COMMUNICATION SYSTEM
INTEGRATED BIPOLAR CIRCUIT
TIME-DIVISION MULTIPLEXER
MULTIPLEXING CAPABILITY
OPTICAL COMMUNICATION
GBIT/S OPERATION

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