Formation of Si–SiO2 stacked-gate structures by plasma-assisted and rapid-thermal processing: Improved device performance through process integration

Abstract
Formation of Si–SiO2 stacked-gate heterostructures requires (i) preparation of Si surfaces prior to interface formation and oxide deposition, (ii) oxide deposition, (iii) polysilicon gate electrode deposition, and generally (iv) post-deposition doping of the gate electrode. Mid- and/or end-process rapid thermal annealing performed in inert or oxidizing ambients may also be necessary to optimize device performance. Four phases in the development of an integrated processing protocol for stacked-gate structures are described in which these steps have been modified, and continuously improved. Process tools have evolved from (i) single-function chambers for (a) surface cleaning/passivation, and (b) thin film deposition, to (ii) dual-function/single process plasma chambers for (a) in-situ surface cleaning and interface formation and (b) oxide deposition, and finally to (iii) multi-function/dual process chambers in which all of the above process steps are done in situ, but by more than one processing technique. This last approach has culminated in chambers which can accommodate (i) low-temperature plasma-assisted interface formation at ∼300 °C, (ii) intermediate-temperature rapid thermal dielectric and polysilicon depositions at 600–800 °C, and (iii) higher-temperature rapid thermal annealing at 900–1000 °C.

This publication has 0 references indexed in Scilit: