A VLSI ATM Cell Processor for Broadband Network Subsystems

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Abstract
Broadband networks are designed for high-bandwidth time-sensitive traffic at speeds more than 10 times the speed of networks today. These speeds place extraordinary stress on the network sabsystems. Typically, subsystems designed for use in the broadband network make use of specialized hardware to provide necessary throughput. Such hardware is usually very restrictive in the types of traffic it can handle. New traffic types often requires changes in the hardware, which increases the cost and design time. To generalize the network interface hardware, we designed a special purpose experimental RISC processor in VLSI with an optimized instruction set, and on-board network communication interfaces. Network data are processed entirely on-chip under the control the the processing unit. The number of traffic types that can be handled is limited only by the time it takes to process the traffic type. This processor is intended for use in experimental broadband networks at speeds of 155-622 Mbps.

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