Efficient input-reordering algorithms for fast DCT

10 October 1991

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 27 (21) , 1973-1975
https://doi.org/10.1049/el:19911222

Abstract

The non-in-place input mapping and the subsequent bit-reversal stage for the computation of the fast discrete cosine transform (DCT) are studied. The redundancies associated with these algorithms are identified and three fast input reordering algorithms are proposed. These new algorithms result in fewer data transfers by a factor of N, reduced storage requirements by a factor of N/2 and an average speed increase of 37%.

Keywords

REDUNDANCIES
REDUCED STORAGE REQUIREMENTS
FAST DCT
NON-IN-PLACE INPUT MAPPING
INPUT-REORDERING ALGORITHMS
DATA TRANSFERS
FAST DISCRETE COSINE TRANSFORM
BANDWIDTH COMPRESSION
SPEED INCREASE
SIGNAL PROCESSING
BIT-REVERSAL STAGE

This publication has 1 reference indexed in Scilit:

DISCRETE COSINE TRANSFORM
Published by Elsevier ,1990