Radiation-Hardened CMOS Devices for Linear Circuit Applications
- 1 January 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 25 (6) , 1465-1468
- https://doi.org/10.1109/TNS.1978.4329554
Abstract
In the past, the use of MOS devices in a radiation environment has normally been restricted to applications requiring a 15 volt power supply or less. This paper discusses a new process for manufacturing high-voltage (30 volt) radiation-hardened CMOS devices for linear circuit applications. Devices have been fabricated which demonstrate hardness above 2 Mrads(Si). This paper also discusses necessary controls and design rules for this process.Keywords
This publication has 3 references indexed in Scilit:
- CMOS Hardness Assurance through Process Controls and Optimized Design ProceduresIEEE Transactions on Nuclear Science, 1977
- Process Optimization of Radiation-Hardened CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1975
- Dependence of MOS Device Radiation-Sensitivity on Oxide ImpuritiesIEEE Transactions on Nuclear Science, 1972