Structure design for submicron MOSFET on ultra thin SOI

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01631918,p. 591-594
https://doi.org/10.1109/iedm.1990.237129

Abstract

In order to overcome the degradation of source-to-drain breakdown voltage (BV/sub dso/) in ultrathin SOI MOSFETs due to parasitic bipolar action, a gate overlapped LDD (lightly doped drain) structure was introduced for drain engineering. By the reduction of drain electric field and parasitic resistance at the source n/sup -/ region, the breakdown voltage was improved while keeping current drivability. The effect of channel doping level on BV/sub dso/ that affects the parasitic bipolar current gain was also investigated. Considering these two factors, guidelines for the structure design of submicron MOSFETs on ultrathin SOI are presented.<>

Keywords

This publication has 1 reference indexed in Scilit:

C.M.O.S. devices fabricated on buried SiO ² layers formed by oxygen implantation into silicon
Electronics Letters, 1978